The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device including a static random access memory.
A static random access memory (referred to hereinafter as SRAM) is a high speed semiconductor memory device comprising a transfer transistor selected by a word line and a pair of CMOS inverters forming a flip-flop connection and connected to a bit line via such a transfer transistor. SRAMs are used extensively in high-speed logic circuits together with a high-speed logic device such as a CMOS circuit.
FIG. 1 shows an equivalent circuit diagram of a typical SRAM 10.
Referring to FIG. 1, the SRAM 10 includes a flip flop circuit FF including therein a first CMOS inverter I1, in which a first load transistor LT1 and a first driver transistor DT1 are connected in series, and a second CMOS inverter 12, in which a second load transistor LT2 and a second driver transistor LD2 are connected in series, wherein it will be noted that a connection node N1 connecting the first load transistor LT1 and the first driver transistor DT1 with each other is connected to a first bit line BL via a first transfer transistor TF1 controlled by a word line WL. Similarly, a connection node N2 connecting the second load transistor LT2 and the second driver transistor LT2 is connected to a second bit line /BL via a second transfer transistor TF2 controlled by the word line WL.
In the SRAM of such a structure, the current drivability of the load transistors LT1 and LT2 driving the driver transistors DT1 and DT2 provides a profound effect on the high-speed operation of the SRAM.
FIG. 2A shows a layout of such an SRAM 10, while FIG. 2B shows the layout of one memory cell corresponding to the SRAM 10 of FIG. 1.
Referring to FIG. 2A, there are formed device regions 10A and device regions 10B on a surface of a silicon substrate in a row and column formation in the state surrounded by a device isolation structure 10I, wherein the memory cell having the circuit construction shown in FIG. 1 is formed by a part of the device region 10A and a part of the device region 10B as shown in FIG. 2B.
Referring to FIG. 2B, it will be noted that the transfer transistors TF1 and TF2 share a gate electrode G1, while the load transistor LT1 and the driver transistor DT1 share a gate electrode G2. Further, the load transistor LT2 and the driver transistor DT2 share a gate electrode G3.
The node N1 of FIG. 1 is provided by a diffusion region shared by the transfer transistor TF1 and the driver transistor DT1, wherein the diffusion region N1 is connected to a corresponding diffusion region N1′ of the load transistor LT1 by way of an interconnection pattern not illustrated. Similarly, the node N2 of FIG. 1 is provided by a diffusion region shared by the transfer transistor TF2 and the driver transistor DT2, wherein the diffusion region N2 is connected to a corresponding diffusion region N2′ of the load transistor LT2 via an interconnection pattern not illustrated.
Further, the gate electrode G2 is connected to the node N2 by way of an interconnection pattern not illustrated, and the gate electrode G2 is connected to the node N1 via an interconnection pattern not illustrated.
(Patent Reference 1) Japanese Laid-Open Patent Application 7-22590 official gazette
(Patent Reference 2) Japanese Patent 3,208,591